During the last five decades since the invention of the MOSFETs, we have seen rapid and stiff advancement in the evolution of integrated circuit engineering.^[1–3] The principal driving force behind this tremendous development has been the downscaling of the dimensions of the MOSFET.^[3,4] The greater the downscale of MOSFET, the higher its packing density becomes, the faster its operation and the lower its power dissipation is.^[5] The perennial downscaling slipstream of MOSFETs has steered eminent execution and low power functioning as prescribed by ITRS, however some newfangled effects in the device performance have also arisen.^[4–6] In particular, a gathering of undesirable sources of difficulties springs up, which are jointly called short channel effects (SCEs) that hinder further advancement in transistor downscaling.^[6] In order to sustain the rate of advancement in device performance with uninterrupted downscaling, alterations to device design and fabrication are the essential requirements. In connection to this, a number of new extended device structures already have been reported in the literature to handle the severe challenges associated with SCEs as well as device efficiency.^[7–15] One of the predominant anticipated solutions in the nanoscale regime to inhibit these SCEs is DG-MOSFET.^[16] However to cope with the device downscaling and quashing the SCEs, there arises the need to allow some relatively thicker gate oxide along with high-k effectuation to exert the electrostatic integrity of the DG MOSFET device.^[7,15] Due to this progression, DG-MOSFET is anticipated to be further investigated to subdue the SCEs.

A multimaterial-based gate structure is anticipated to provide further improvement in the performance of DG MOSFET since it may create a step potential profile to screen the effect of the drain on the channel.^[12,13] Another possible solution to suppress SCEs is by using gate stack. If aforementioned solutions are combined in order to improve the performance of DG MOSFET then it may prove to be an effective option over the existing technology. There exist several reports that establish the superiority of the performance of TM DG MOSFET and gate stack structures.^[12–15] Razavi and Orouji^[12] proposed TM-DG MOSFET structure and through numerical simulation results they showed that SCEs such as drain-induced barrier lowering (DIBL) and hot carrier effect are reduced significantly in comparison with conventional DG MOSFET. They also demonstrated that TM-DG MOSFET leads simultaneously to the enhancement of transconductance and the reduction of drain conductance which itself leads to higher DC gain than the classical DG MOSFET. Pradhan et al.^[13] reported a simulation-based study for the performance differences among six dissimilar gate stacked device structures by utilizing gate and channel engineering. They also considered the gate stack TM DG MOSFET for the simulation purpose and established that TM DG MOSFET with gate stack structures improves DIBL significantly. Alamgir et al.^[14] investigated the performance of DG-MOSFET with high-k stack on both the top and bottom gates using numerical simulation results. They observed that higher drain current in the low and high drain voltage regions, as well as lower threshold voltage and improved subthreshold swing can be yielded by considering their proposed structure. Jin et al.^[15] presented an analytical-model-based study for surface potential, threshold voltage, subthreshold current and subthreshold swing of symmetrical gate stack dual gate strained silicon MOSFETs. They showed that the high-k region on the oxide layer exhibits reduced SCE.

Therefore, based on the literature it can be concluded that pertaining to the scaling down of the device thickness, triple material gate stack structure is anticipated to be a more effective option over existing DG MOSFET device. To the best of my knowledge, so far in the literature analytical modeling and simulation-based study of TM DG MOSFET with gate stack have not been done. Hence in the present paper, combining the advantages of high-k gate stack and triple material structure, a new compact analytical model for triple material symmetrical gate stack (TMGS)-DG MOSFET is presented. In this proposed device structure, the front and back gate electrode each comprising three materials with different work functions and symmetrical high-k gate stack are considered for developing the compact analytical model and numerical simulation. Moreover, the channel of the simulated model is adopted to be lightly doped in order to increase the mobility of the charge carriers and stave off the problem of threshold voltage variation due to random fluctuation of dopant atoms. The result analysis is based on the solution of two dimensional (2D) Poisson’s equation with the appropriate limit specifications employing 2D ATLAS™ device simulation tool.^[17]

The schematic device structure of TMGS-DG MOSFET used for analysis and simulation is shown in Fig. 1, where L (L = L₁ + L₂ + L₃), t_si, t_ox, and t_k are gate length, channel thickness, thickness of gate oxide and thickness of material with large dielectric constant, respectively. The x and y axes of the schematic structure are considered to be along the channel length and channel thickness, respectively.

Fig. 1.

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	Fig. 1. Schematic diagram of TMGS DG MOSFET, where L (L = L1 + L2 + L3), tsi, tox, and tk are gate length, thickness of silicon channel, thickness of gate oxide, and thickness of high dielectric constant material, respectively.

The gate electrode of the DG MOSFET is considered to be made up of three materials having different work functions ϕ_m1, ϕ_m2, and ϕ_m3 (such that ϕ_m1 > ϕ_m2 > ϕ_m3) and deposited over the respective lengths L₁, L₂, and L₃ on the gate oxide layer. The gate material placed at the source end with the highest work-function i.e., ϕ_m1 forms a control gate, the middle material with intermediate work-function value ϕ_m2 forms a first screen gate, and the remaining material with the lowest work function ϕ_m3 placed at the drain side of the gate forms a second screen gate. In the present work tungsten disilicide (WSi₂, ϕ_m1 = 4.8 eV), Hf_0.27Ta_0.58N_0.15 (ϕ_m2=4.6 eV), and Hf_0.40Ta_0.46N_0.14 (ϕ_m3 =4.4 eV) are used as the materials for control gate, first and second screen gates, respectively. The gate terminal of the TMGS-DG MOSFET device is made by tying together control and screen gates in order to feed the device with the same gate voltage V_gs. In the proposed structure, high-k gate stack is used in order to combat the SCEs therefore in place of t_ox effective gate oxide thickness (t_eff) is used. t_eff can be given as^[15]

In this section, we present some theoretical results obtained by the proposed model that is validated by comparing the theoretical results with the numerical simulation data obtained by using the ATLAS™ device simulator. The drift-diffusion model has been used for carrier transport, and classical Fermi–Dirac statistics model is used for the numerical simulation.^[24] To integrate the effect of high electric field in the device channel, the field dependent mobility model has been implemented in the ATLAS™ simulation.^[25,26] Further, the ratio of lengths of regions I, II, and III is taken to be L₁ : L₂ : L₃: 1 : 1 : 1 for all the computations. The p-type substrate concentration is taken to be uniformly doped with a doping concentration of N_a = 1 × 10¹⁶ cm⁻³ in all the three regions under different gate metal contacts. The source and drain regions are both assumed to be heavily doped with doping concentration of N_S/D = 1 × 10²⁰ cm⁻³. The dielectric constant value of high-k material is taken to be 20. The typical values of t_si, t_ox, and t_k are taken to be 20 nm, 2 nm, and 4 nm respectively.

Figure 2 shows the variations of surface potential of TMGS-DG MOSFET along the gate length for different values of drain-to-source voltage (V_ds). It can be clearly seen from the figure that the area under the control gate is effectively screened from the variations in V_ds, thereby giving rise to negligible DIBL effect in the device due to the presence of the two screening gates. Further, it may also be observed from the figure that the position of minimum channel potential lies under the control gate, which justifies the assumption that we have made for modeling the threshold voltage. The variations of threshold voltage with gate length for different values of V_ds are plotted in Fig. 3. It can be seen from the figure that for longer gate length devices, threshold voltage varies little with the drain bias compared with the corresponding shift of threshold voltage for shorter gate length devices.

Fig. 2.

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	Fig. 2. Variations of channel potential with position along the channel length for different values of drain-to-source voltage (Vds).

Fig. 3.

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	Fig. 3. Variations of threshold voltage with gate length (L) for different values of drain-to-source voltage (Vds).

Figure 4 demonstrates the variations of threshold voltage with gate length for different values of silicon thickness (t_si). It is noteworthy here that for the lower values of t_si, the roll-off in the threshold voltage is relatively low in comparison with that for the higher channel thickness. It may be due to the improvement in the gate electrostatics on the channel with the decrease in t_si.

Fig. 4.

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	Fig. 4. Variations of threshold voltage with gate length (L) for different values of silicon film thickness tsi.

Figure 5 shows the variations of the threshold voltage with channel lengths for different values of gate-oxide thickness (t_ox). It can be observed from the figure that the device with lower t_ox shows better suppression of SCEs.

Fig. 5.

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	Fig. 5. Variations of threshold voltage with gate length (L) for different values of gate-oxide thickness (tox).

Figure 6 shows the variations of threshold voltage with channel length (L) for different values of stack layer thickness (t_k). The threshold voltage roll-off is higher for large value of t_k. It may further be noted that if we compare Fig. 5 with Fig. 6, then it may be observed that the effect of t_k oversees the effect of t_ox on the threshold voltage variation. Even the threshold voltage roll-off is improved in the case of larger value of t_k therefore in the case of TMGS-DG MOSFET gate stack oxide acts as a controlling gate oxide.

Fig. 6.

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	Fig. 6. Variations of threshold voltage with the gate length (L) for different values of stack layer thickness (tk).

Figure 7 shows the effects of change of high-k stack material on the threshold voltage of the device with different gate lengths. Three different dielectric materials are considered i.e., HfO₂, Al₂O₃, and SiO₂ with largest value of dielectric constant for HfO₂ and least value for SiO₂. It can be observed from the figure that for the material with high dielectric constant threshold voltage, the roll-off is considerably reduced. It may be due to the fact that increasing dielectric constant of the stack material can lead to a decrease in the effective gate oxide thickness t_eff (Eq. (1)), which may result in an efficient suppression of SCEs. This implies that the improved gate controllability can be achieved by using material with high dielectric constant to establish the suitability of TMGS-DG MOSFET over conventional DG MOSFET.

Fig. 7.

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	Fig. 7. Variations of threshold voltage with gate length (L) for different stack materials HfO2, Al2O3, and SiO2.

In the present paper, channel potential and threshold voltage of DG-MOSFET is modeled analytically. A detailed study to see the effects of gate stack on the threshold voltage of TMGS DG-MOSFET and other important parameters is performed in detail. The model results are found to be well matched with the ATLAS numerical simulation results for different values of drain bias, silicon film thickness, gate-oxide thickness, stack layer thickness and stack materials.